1. Field of the Invention
The present invention relates to a static-type semiconductor memory device (hereinafter referred to as SRAM (Static Random Access Memory)), in particular, to a memory cell structure of an SRAM.
2. Description of the Background Art
FIGS. 13 to 16 show a layout of memory cells of a conventional SRAM. In these figures two memory cells 1 and a well contact cell 2 are shown. In the case that a well contact region is formed in, respectively, all of the memory cells 1, the area of the memory cell 1 increases and, therefore, a well contact cell 2 is formed for a plurality of memory cells 1 so as to achieve the reduction of the area of the memory cell array.
As shown in FIG. 13, memory cells 1 are arranged, respectively, above and below well contact cell 2. Memory cells 1 and well contact cell 2 both have an n well in the middle and have p wells on both the right and left sides of this n well.
One memory cell 1 has six MOS Metal Oxide Semiconductor) transistors. In more detail, memory cell 1 has n type access MOS transistors Q1, Q2, n type driver MOS transistors Q3, Q4 as well as p type load MOS transistors Q5 and Q6.
In upper memory cell 1, access MOS transistor Q1 is formed at a part where a diffusion region 40i and a polysilicon layer 3b cross, access MOS transistor Q2 is formed at a part where a diffusion region 40a and a polysilicon layer 3c cross, driver MOS transistor Q3 is formed at a part where diffusion region 40i and a polysilicon layer 3d cross, driver MOS transistor Q4 is formed at a part where diffusion region 40a and a polysilicon layer 3a cross, load MOS transistor Q5 is formed at a part a diffusion region 40d and polysilicon layer 3a cross and load MOS transistor Q6 is formed at a part where a diffusion region 40e and polysilicon layer 3d cross.
In lower memory cell 1, access MOS transistor Q1 is formed at a part where a diffusion region 40k and a polysilicon layer 3j cross, access MOS transistor Q2 is formed at a part where a diffusion region 40c and a polysilicon layer 3k cross, driver MOS transistor Q3 is formed at a part where diffusion region 40k and a polysilicon layer 3l cross, driver MOS transistor Q4 is formed at a part where diffusion region 40c and a polysilicon layer 3i cross, load MOS transistor Q5 is formed at a part where a diffusion region 40g and polysilicon layer 3i cross and load MOS transistor Q6 is formed at a part where a diffusion region 40h and polysilicon layer 3l cross.
Well contact cell 2 has diffusion regions 40b, 40f, 40j and polysilicon layers 3e, 3f, 3g and 3h. 
FIG. 14 shows a layout of contact parts 5, 5e to 5f and 5i. As shown in FIG. 14, predetermined regions in diffusion regions 40a to 40k are electrically connected to upper layer wires via contact part 5, 5e to 5f and 5i. In addition, a predetermined polysilicon layer from among polysilicon layers 3a to 3l is also electrically connected to an upper layer wire, or the like, via contact part 5.
P+ diffusion regions 40b and 40j are fixed at the ground potential via contact parts 5e and 5f and, thereby, the p well is fixed at the ground potential. In addition, n+ diffusion region 40f is fixed at the power supply potential via contact part 5i and, thereby, the n well is fixed at the power supply potential.
Polysilicon layers 3e and 3f are dummy layers for securing the periodicity of polysilicon layers of upper memory cell 1 in FIG. 13. In addition, polysilicon layers 3g and 3h are dummy layers for securing the periodicity of polysilicon layers of lower memory cell 1 in FIG. 13.
FIG. 15 shows first metal wire layers 7, with first via holes 6, formed in a layer above polysilicon layers 3a to 3l. 
As shown in FIG. 15, first metal wire layers 7 are formed so as to make connections between contact parts 5 or between contact parts 5 and contact parts 5e, 5f and 5i while first via holes 6 are created at predetermined positions in first metal wire layers 7.
FIG. 16 shows a layout of second metal wire layers 9 and third metal wire layers 10a to 10e, with second via holes 8, formed in a layer above first metal wire layers 7.
As shown in FIG. 16, first metal wire layers 7 and second metal wire layers 9 are connected via first via holes 6 while second metal wire layers 9 and third metal wire layers 10a to 10e are connected via second via holes 8.
In the above conventional SRAM, as shown in FIG. 13, insulation regions are formed between diffusion regions 40b, 40f, 40j within well contact cell 2 and diffusion regions 40a, 40c, 40e, 40g, 40i, 40k within memory cell 1 so as to separate these regions. Therefore, the length L of well contact cell 2 in the upper and lower direction of FIG. 13 becomes larger than the length L1 of memory cell 1 so that the areas of memory cell 1 and well contact cell 2 become different.
In addition, by separating diffusion regions in well contact cell 2 as described above, the regularity of the pattern (in particular, diffusion region pattern or polysilicon layer pattern) which is repeated regularly among adjoining memory cells 1 is disturbed in well contact cell 2. That is to say, the existence of well contact cell 2 disturbs the periodicity of the pattern layout.
Diffusion regions 40a to 40k and polysilicon layers 3a to 3l are usually formed by using a photolithographic technology and in the case that the periodicity of the pattern layout is disturbed as described above, a dispersion of the size of the pattern is easily caused at the time of the formation of each pattern. Therefore, a problem arises that the dispersion of the transistor characteristics is easily caused.
Here, as shown in FIG. 13, by arranging polysilicon layers 3e, 3f, 3g and 3h as dummy layers, the fluctuation of the periodicity of the polysilicon layers in memory cells 1 can be restricted to a certain degree. However, this effect becomes smaller together with the miniaturization of memory cells 1 and the effect is not very apparent for the miniaturized memory cells 1.
In addition, as for a layout wherein the periodicity of the pattern of memory cells 1 is taken into consideration, the layout shown in U.S. Pat. No. 6,128,208 can be cited. According to the invention described in this reference, however, well contact cell 2 is not provided and the idea of the layout in the case that well contact cell 2 is provided is not disclosed in this reference.
The present invention is provided in order to solve the above problem. A purpose of the present invention is to prevent the periodicity of the pattern layout of diffusion regions, polysilicon layers, or the like, from being disturbed in an SRAM which has well contact cells and memory cells.
An SRAM (static-type semiconductor memory device) according to the present invention comprises a plurality of memory cells and well contact cells. The memory cells do not have a well contact region and provided over a plurality of wells for storing data. The well contact cells for fixing the potential of the wells are provided over a plurality of wells so as to adjoin memory cells. The area of a memory cell and the area of a well contact cell are equal.
By making the area of a memory cell and the area of a well contact cell equal, as described above, a pattern similar to that within a memory cell, such as for diffusion regions or for polysilicon layers (gates), can be formed in the same manner in a well contact cell. Thereby, the periodicity of the above pattern can be prevented from being disturbed in well contact cells.
A memory cell has a first diffusion region of a first conductive type while a well contact cell has a second diffusion region of a second conductive type for fixing the potential of the well. In this case, it is preferable to connect the first and second diffusion regions within the well contact cell via a third diffusion region.
By linking a diffusion region from within a memory cell to within a well contact cell in this manner, the diffusion region can be extended from the inside of a memory cell to the inside of a well contact cell in a contiguous manner. For example, the diffusion region can be formed so as to cross the well contact cell. As a result, it becomes unnecessary to separate a diffusion region inside of a well contact cell, as opposed to in a prior art, and the periodicity of the diffusion region pattern can be prevented from being disturbed in a well contact cell.
A well contact cell has a first conductive layer which extends above the third diffusion region and fixes the first conductive layer to the ground potential.
In this manner, by providing a first conductive layer within a well contact cell, for example, the periodicity of the pattern of the conductive layers which become the gates of MOS transistors within a memory cell can be secured. At this time, an element of a similar structure to that of a MOS transistor is formed of the first conductive layer and the above first to third diffusion regions within the well contact cell. Even though this element has a similar structure to a MOS transistor, this element does not operate in the same manner as a MOS transistor. In the present invention such an element is referred to as a pseudo transistor. Though this pseudo transistor is considered to not operate as a transistor under usual conditions, the pseudo transistor can be prevented without fail from mistakenly operating by fixing the first conductive layer that corresponds to the gate of the pseudo transistor at the ground potential as described above. Thereby, the pseudo transistor can be prevented from causing negative effects to the memory cell so that the normal operation of the memory cell can be secured.
The SRAM of the present invention is provided with bit lines. Then, the above first diffusion region is connected to a bit line. In such a case, by fixing the first conductive layer at the ground potential, as described above, the well contact cell and the bit line can be electrically isolated.
The above plurality of wells include a first well of the first conductive type (corresponding to an n well in the example of FIG. 1) and a second well of the second conductive type (corresponding to a p well in the example of FIG. 1). In this case, the first, second and third diffusion regions (corresponding to predetermined diffusion regions within diffusion region 4a in the example of FIG. 1) are positioned in the second well, the well contact cell is positioned in the first well and has a fourth diffusion region (comprising to an n type diffusion region within diffusion region 4d in the example of FIG. 1) of the first conductive type which is positioned in the first well and is for fixing the potential of the first well and the memory cell has a fifth diffusion region (corresponding to a p type diffusion region within diffusion region 4d in the example of FIG. 1) of a second conductive type which is located in the first well. Then, the fourth diffusion region and the fifth diffusion region are connected within the well contact cell via a sixth diffusion region (corresponding to an n type diffusion region within diffusion region 4d beneath polysilicon layer 3f in the example of FIG. 1), a second conductive layer (corresponding to polysilicon layer 3f in the example of FIG. 1) is formed above the sixth diffusion region and the fourth diffusion region, the fifth diffusion region and the second conductive layer are fixed at the power supply potential.
As described above, a pseudo transistor is formed on the first well of a different conductive type (polarity) from that of the second well and, in this case, the pseudo transistor can be prevented, without fail, from operating by fixing the fourth diffusion region, the fifth diffusion region and the second conductive layer at the power supply potential. Thereby, the normal operation of the memory cell can be secured.
The plurality of wells include the first well of the first conductive type and the second well of the second conductive type. A memory cell has a first diffusion region of the first conductive type and a third diffusion region of the second conductive type while a well contact cell has a second diffusion region of the second conductive type for fixing the potential of the well and a fourth diffusion region of the first conductive type. At this time the first and second diffusion regions are located in the second well while the third and fourth diffusion regions are positioned in the first well. Then, the first and second diffusion regions are isolated within the well contact cell while the third and fourth diffusion regions are connected within the well contact cell via a fifth diffusion region.
In this manner, parts of diffusion regions may be extended from the inside of a memory cell to the inside of a well contact cell while other parts of diffusion regions may be isolated within the well contact cell. In this case, though the periodicity of the diffusion region pattern may be some what disturbed in a part wherein diffusion regions are isolated, the periodicity of the diffusion region pattern can be secured in the parts where the diffusion region is formed to be contiguous from the inside of a memory cell to the inside of a well contact cell. Accordingly, the periodicity of the pattern can be secured in comparison with the prior art.
The first conductive layer is formed above the region between the above first and second diffusion regions and the second conductive layer is formed above the fifth diffusion region. In this case, it is preferable to fix the second conductive layer, the third diffusion region and the fourth diffusion region at the power supply potential.
Since the first and second diffusion regions are isolated from each other, as described above, a pseudo transistor is not formed of the first conductive layer and these diffusion regions. Accordingly, the first conductive layer need not be fixed at the ground potential. However, the second conductive layer, the third diffusion region, the fourth diffusion region and the fifth diffusion region form a pseudo transistor. Therefore, by fixing the second conductive layer, the third diffusion region and the fourth diffusion region at the power supply potential, the above pseudo transistor can be prevented, without fail, from operating.
The SRAM is provided with bit lines and the first diffusion region is connected to a bit line. In this case, by isolating the first and second diffusion regions from each other, as described above, the bit line and the well contact cell can be electrically isolated.
Memory cells may be arranged on both sides of the above well contact cell. In addition, a plurality of well contact cells may be arranged adjoining each other. In either case the periodicity of the pattern layout can be secured.
It is preferable that the above plurality of well contact cells include first and second well contact cells wherein the first well contact cell has a second diffusion region and a seventh diffusion region of the second conductive type which is connected to this second diffusion region while the second well contact cell has an eighth diffusion region of the second conductive type that is connected to the seventh diffusion region and extends within the first well contact cell.
In this manner, extending a diffusion region from the inside of the first well contact cell to the inside of the second well contact cell in a contiguous manner, the periodicity of the pattern layout can be secured from among the well contact cells.
It is preferable to arrange the memory cells and the well contact cells in the direction (direction of extension of each well) perpendicular to the direction along which a plurality of wells are arranged. In this case that, by extending diffusion regions in the direction of the extension of each well, a diffusion region can be formed in a contiguous manner from the inside of a memory cell to the inside of a well contact cell so that the periodicity of the diffusion region pattern can be secured. Accordingly, the present invention is useful for a memory cell array which has the cell arrangement as described above.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.